The present invention relates to a video RAM as a dual port memory, and more particularly to a video RAM which is adaptable to a high speed system clock and a serial data output method thereof.
With the increased use of potable computers like a note book, the video RAMs are now very widely used in computers. A video RAM is a dual port memory which can be asynchronously utilized by adding the function of a data register which is capable of transferring data at a high speed to the function of a normal dynamic RAM. One conventional video RAM and its operation method are disclosed in U.S. patent application Ser. No. 4,498,155 entitled "Semiconductor Integrated Circuit Memory Device With Both Serial And Random Access Arrays" filed Feb. 5, 1985. Such a video RAM is designed to be able to connect a dynamic RAM port to a CPU and a high speed SAM port to an external system such as a CRT or a video camera, so that it has excellent system applicability and can have wide application. In order to diversify its functions and to store more information, highly integrated video RAM are continuing to be developed.
In a high performance graphic system, each device is required to operate in response to a high frequency in order to effectively perform the graphic interface between the computer and its user. Thus, the internal circuits in the video RAM should also operate in response to the high speed system clock supplied from the system. Such operation depends on whether the data transferred through a data I/O line within the video RAM can respond to the system clock.
FIG. 1 briefly shows the circuit elements related to data I/O lines in a conventional video RAM. FIG. 2 is an operational timing diagram of the FIG. 1 circuit. In FIG. 1, serial column gates 3 for transferring data is formed between a data register 2 and a serial data I/O line SIO. One serial column gate 3A has four serial column gate electrodes 4 commonly controlled by a serial column selection line SCSLi and another has four serial column gate electrodes 4 commonly controlled by a serial column selection line SCSLj. The serial data I/O line SIO is composed of one of the lines to receive data transferred from four serial column gates 3 in response to a single enabled of a serial column selection signal. The data on the serial data I/O line SIO is multiplexed through a multiplexer 6 and is amplified through a sense amplifier 8. The output of the sense amplifier is applied to a latch unit 10 which is controlled by the control signal .phi.PSOT, and the output of the latch unit 10 is applied to a latch output unit 12 which is controlled by the control signal .phi.SOT and then outputs data to externally.
Referring to the timing diagram of FIG. 2, the operational characteristic of the FIG. 1 circuit will now be described. The serial address is incremented at the falling edge of the serial clock SC. The corresponding serial column selection line is enabled on the basis of the serial address. With the enable of the serial column selection line, data stored in the data register 2 is outputted to the serial data I/O line SIO, and the sense amplifier 8 thus outputs the amplified signal SDO. Referring to FIG. 2, the signal SDO generated at the falling edge of the nth serial clock SC is latched at the falling edge of the (n+1)th serial clock SC by the control signal .phi.PSOT, and is then output as valid data at the rising edge of the (n+2)th serial clock SC external from the chip. Such a construction having a data I/O line as shown in FIG. 1 is designed to read out data from the memory cell through a single data I/O line. Additional time is required to sense data.
However, such construction consumes large amounts of time, as described hereinafter through the data I/O line because this depends on the minimum time required in developing the serial data I/O line from the activation of the serial column selection line SCSL. Also, additional time is required for precharging and equalizing the data I/O line is required in order to prepare next read cycle, because the precharge time depends on the time required in equalizing the amplified data I/O line. In addition, extra time is required for latching the valid data which depends on the time required in generating the signal SDO that is latched by the control signal .phi.PSOT. Since the FIG. 1 circuit is designed in consideration of the above-mentioned timing requirements, the time interval between respective serial clocks and the operation cycle is increased. This time consumption affects the operation cycle of the whole chip, and thus the cycle time is relatively increased as compared to the serial clock. This causes another in that it is difficult to transfer data at a high speed from the data register to the external display device.